In general components, for example, electronic components or devices, micro-electronic chips, memory chips or other integrated circuits (IC), are usually tested before they are delivered to a customer. Testing may be performed in order to prove and ensure the correct functional capability of the devices. The tests are usually performed by means of an automated test equipment or test system. Examples for such automatic test equipment are the Verigy V93000 SOC for testing system on a chip and system on a package, the V93000 HSM high speed memory tester (HSM) for testing high speed memory devices and the Verigy V5000 series. The first is a platform for testing systems on a chip, systems on a package and high-speed memory devices. The latter is for testing memory devices including flash memory and multi-chip packages at wafer sort and final test.
During testing these devices under test are exposed to various types of stimulus signals from an ATE. The responses from such devices under test are measured, processed and compared to an expected response by the ATE. Testing may be carried out by automated test equipment, which usually performs testing according to a device specific test program or test flow. Such an automatic test system may comprise different drivers for driving certain stimuli to a DUT, in order to stimulate a certain expected response from the device under test. Receiver units of the ATE may analyze the response and may thereby generate a pass-fail information regarding the measured device.
Components or devices that have to be tested may comprise a high number of pins, for example, input and output pins to be tested. Therefore, the number of drivers and receivers which are needed for testing can be high. As a consequence, expenses for such a test system can be high. With a shared driver topology in a test system the number of drivers for testing DUTs can be reduced, since a plurality of DUTs can be driven in a serialized manner by a single driver unit. Therefore, the number of drivers and consequently the costs for testing a DUT can be reduced. So far, the shared driver topology is only applied to input pins of DUTs. Accordingly, a large number of test equipment receivers are required when testing multiple devices.